An embodiment of the invention is directed at the control of one or more clocks under which electronic circuits operate. These clocks provide a way for events affecting (or caused by) the circuit to be sequenced reliably. For example, digital circuits such as microprocessors, digital signal processors and memories rely on clocks to synchronize and drive their operations.
One long-standing trend in the development of electronic circuits is the increase in clock speeds; another is the increase in the size of electronic circuits relative to the size of the components that make up the circuit. Both of these trends increase the difficulty of providing stable, useful clock signals to all parts of the circuit (or system) that need them. Transmitting the multi-gigahertz clock signals used in modern circuits from one place in the system to another often results in degradation of the signals, so that (for example) a circuit designed to work with a 50% duty cycle clock might receive a 20% or 70% duty cycle clock. The degraded clock may cause deleterious effects ranging from increased power usage to unstable or incorrect circuit operation.
A number of techniques have been developed to stabilize or correct clock signal waveforms. For example, duty cycle correctors are described in A portable digital DLL for high-speed CMOS interface circuits by Garlepp et al. (IEEE Journal of Solid State Circuits, vol. 34, no. 5 (May 1999)) and A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM by T. H. Lee et al. (IEEE Journal of Solid State Circuits, vol. 29, no. 12 (December 1994)).